1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a hierarchical bit line structure.
2. Description of the Background Art
In conventional semiconductor memory devices, bit lines are hierarchically arranged in order to prevent the level of the bit line from being reduced due to a cut-off leakage current. For example, Japanese Patent Laid-Open Publication No. 6-176592 (p. 2, FIG. 2) discloses a mask ROM having a contact, as an example of such a semiconductor memory device having a hierarchical bit line structure.
FIG. 13 is a block diagram illustrating a configuration of a conventional mask ROM. The mask ROM 50 comprises a memory cell array 51, an address buffer 52, a row decoder 53, a column decoder 54, and a read circuit 55.
The memory cell array 51 comprises (m×n) subarrays 57 (MS1_1 to MSm_n) arranged in a matrix, m block select lines SL4_1 to SL4_m, (y×m) word lines WL1_1 to WLy_m, and n main bit lines MBL1 to MBLn. The subarrays 57 (MSi_1 to MSi_n) provided on an i-th row are each connected to the block select line SL4_i and the word lines WL1_i to WLy_i. The subarrays 57 (MS1_j to MSm_j) provided on a j-th column are each connected to the main bit line MBLj.
The address buffer 52 outputs an externally input address to the row decoder 53 and the column decoder 54.
Based on the address signal output from the address buffer 52, the row decoder 53 selects one block select line (e.g., SL4_i) from the block select lines SL4_1 to SL4_m, and one word line (e.g., WLk_i) from the word lines WL1_i to WLy_i.
Based on the address signal output from the address buffer 52, the column decoder 54 selects one main bit line (e.g., MBLj) from the main bit lines MBL1 to MBLn and causes the selected main bit line (MBLj) to be in conduction with the read circuit 55.
The read circuit 55 is connected to the column decoder 54. The read circuit 55 has a function of amplifying an amplitude of a signal on the main bit line MBLj selected by the column decoder 54 and outputting data corresponding to a level of the main bit line MBLj to the outside, a function of precharging or discharging the selected main bit line MBLj, and a function of supplying charge to the main bit line MBLj to compensate for charge lost due to leakage. The read circuit 55 outputs H-level data when a voltage of the main bit line MBLj is at the H level, and L-level data when the voltage of the main bit line MBLj is at the L level.
Note that the above-described plurality of subarrays MS1_1 to MSm_n are all similarly configured, and therefore, only the subarray MS1_1 will be hereinafter described.
FIG. 14 is a circuit diagram illustrating a configuration of the subarray 57 of FIG. 13. The subarray 57 comprises y memory cells MC1 to MCy each composed of an N-channel MOS transistor and a block select transistor NT1 composed of an N-channel MOS transistor.
The gate electrodes of the memory cells MC1 to MCy are connected to the word lines WL1_1 to WLy_1, respectively, and the source electrodes thereof are connected to a ground voltage. The drain electrodes of the memory cells MC1 to MCy are each connected via a contact (not shown) to a sub-bit line SBL1_1 when data to be stored is “0”, and are not connected to the sub-bit line SBL1_1 when data to be stored is “1”. For example, as illustrated in FIG. 14, the memory cells MC1 and MC2 stores data “0” and the memory cell MCy stores data “1”.
On the other hand, the gate electrode of the block select transistor NT1 is connected to the block select line SL4_1, the source electrode thereof is connected to the sub-bit line SBL1_1, and the drain electrode thereof is connected to the main bit line MBL1.
FIG. 15 is a timing diagram of the conventional semiconductor memory device. In FIG. 15, an address AD1 is, for example, an address which specifies the memory cell MC1 in the subarray MS1_1 of FIG. 13, and an address AD2 is, for example, an address which specifies the memory cell MC1 in another subarray (MS1_i) which is located on a column different from that of the subarray MS1_1. A time period for which a clock of FIG. 15 is at the L level is a time period for which a precharge operation is performed. A time period for which the clock is at the H level is a time period for which a read operation is performed. Hereinafter, referring to FIG. 15 in combination with FIG. 14, a data read operation in the conventional semiconductor memory device will be described.
(1) Time period before time T1
Since the subarray MS1_1 is in the non-selected state before time T1, the voltages of the block select line SL4_1, the word lines WL1_1 to WL1_y, and the main bit line MBL1 connected to the subarray MS1_1 are all held at the L level. As illustrated in FIG. 14, since the sub-bit line SBL1_1 is not connected to any power source lines, the voltage of the sub-bit line SBL1_1 is in the floating state (high impedance state). Note that, since the sub-bit line SBL1_1 is not connected to the gate electrodes of any MOS transistors, there are no problems, such as an unstable transistor operation and the like.
(2) Time period from time T1 to time T2
Initially, when the address AD1 is inputted at time T1, the row decoder 53 selects the block select line SL4_1 and causes the block select line SL4_1 to go to the H level. Thereby, the block select transistor NT1 in the subarray MS1_1 goes to the ON state, so that the main bit line MBL1 is caused to be in conduction with the sub-bit line SBL1_1.
Next, the main bit line MBL1 and the sub-bit line SBL1_1 are charged by the precharge function of the read circuit 55, to go to the H level. Note that, for this time period, the other block select lines (SL4_2 to SL4_m of FIG. 13) are all held at the L level.
(3) Time period from time T2 to time T3
When the clock goes to the H level, the row decoder 53 selects the word line WL1_1 based on the address AD1, and causes the voltage of the word line WL1_1 to go to the H level. In this case, the memory cell MC1 goes to the ON state. Since the drain electrode of the memory cell MC1 is connected to the sub-bit line SBL1_1, when the memory cell MC1 goes to the ON state, charge accumulated on the sub-bit line SBL1_1 and the main bit line MBL1 are discharged through the source electrode of the memory cell MC1. Therefore, the voltages of the main bit line MBL1 and the sub-bit line SBL1_1 go to the L level as illustrated with solid lines in FIG. 15. As a result, the read circuit 55 outputs L-level data to the outside, corresponding to the voltage of the main bit line MBL1.
On the other hand, it is assumed that the drain electrode of the memory cell MC1 is not connected to the sub-bit line SBL1_1. In this case, charge accumulated on the sub-bit line SBL1_1 and the main bit line MBL1 is not discharged through the memory cell MC1 even when the memory cell MC1 goes to the ON state, and therefore, the sub-bit line SBL1_1 and the main bit line MBL1 are held at the H level as illustrated with dashed lines in FIG. 15. As a result, the read circuit 55 outputs H-level data to the outside, corresponding to the voltage of the main bit line MBL1.
(4) Time period from time T4 to time T7
Thereafter, also with respect to the address AD2 input at time T4, stored data is read out in a manner similar to that for the above-described time period from time T1 to time T4. Note that, in the example of FIG. 15, since the address AD2 is an address which specifies the memory cell MC1 in a subarray MS1_i on a column different from that of the subarray MS1_1, the block select line SL4_1 is held at the H level for this time period. The voltage of the word line WL1_1 is changed to the H level for a data read time period from time T5 to time T6 since the word line WL1_1 is selected by the row decoder 53.
As described above, the conventional mask ROM is configured so that a plurality of memory cells provided along a single main bit line are not connected directly to the main bit line, but are divided into subarrays and are connected via respective sub-bit lines. Therefore, after the sub-bit line is precharged, accumulated charge is discharged due to an off-leakage current from memory cells (e.g., MC1 and MC2) connected to the sub-bit line, so that the level of the main bit line can be significantly suppressed from being reduced. Therefore, even in a miniaturization process having an increase in the off leakage current, a large scale memory array can be achieved.
In the above-described semiconductor memory device, a main bit line is connected to a sub-bit line via a block select transistor. Therefore, when the main bit line is discharged, charge accumulated on the main bit line is discharged via the block select transistor from the source electrode of a memory cell. Note that, in order to reduce the area of the semiconductor memory device, a small-size transistor is used in a memory cell. The sub-bit line is charged via the main bit line and the block select transistor by a precharge transistor in a read circuit.
In the case where such a conventional semiconductor memory device is used with a low voltage, when a main bit line is discharged, the substrate bias effect is significant in a block select transistor, so that the current drive capability of the block select transistor to discharge the main bit line is reduced. When a sub-bit line is charged, the influence of the substrate bias effect in the block select transistor reduces the current drive capability of the block select transistor to charge the sub-bit line, so that high-speed precharge cannot be performed. Therefore, it is not possible to read out stored data with high speed.
Therefore, a method of reducing a threshold voltage of a portion of transistors during manufacture, and a method for reducing the influence of the substrate bias effect and on-resistance by increasing a gate voltage of a portion of transistors, have been proposed.
However, in the former method of reducing the threshold voltage, a dedicated production step is required in addition to ordinary production steps. On the other hand, in the latter method of increasing the gate voltage, the area of a semiconductor memory device is increased by adding a booster circuit. Therefore, even when either of the methods is employed, the manufacturing cost of a semiconductor memory device increases.